Semiconductor device and method of manufacturing the same

ABSTRACT

In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a division of application Ser. No. 10/807,303, filed Mar. 24,2004 (now U.S. Pat. No. 6,930,359), which is a division of applicationSer. No. 09/713,251, filed Nov. 16, 2000 (now U.S. Pat. No. 6,724,045),both of which are incorporated in their entirety herein by reference.This application is also based upon and claims priority from priorJapanese Patent Application No. 11-327916, filed Nov. 18, 1999, theentire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device in which aplurality of semiconductor elements have a SOI (Silicon On Insulator)-Silayer and a method of manufacturing the same. More particularly, thepresent invention relates to a structure of an element isolation filmand a method of manufacturing the same.

In a conventionally-known semiconductor device, a CMOS element and abipolar element are integrally formed on a SOI substrate (U.S. Pat. No.5,212,397). The SOI substrate is constituted of a silicon semi-conductorsubstrate (Si-sub) 1 and a buried oxide film (BOX) 2 formed thereon, asshown in FIG. 23. The buried oxide film 2 is formed by doping oxygenions into the semiconductor substrate. The SOI substrate has a bipolarregion 9 and a CMOS region 10. CMOS elements 7 and 8 are formed in theCMOS region 10, whereas a bipolar element is formed in the bipolarregion 9. More specifically, the CMOS elements 7 and 8 are formed in athin single crystalline silicon layer 3 formed on the buried oxide film(BOX) 2 within the CMOS region 10. The buried oxide film (BOX) 2 isdeeply etched within the bipolar region 9. Within the etched region ofthe buried oxide film (BOX) 2, a thick single crystalline silicon layer4 is formed by epitaxial deposition. A semiconductor element (bipolarelement) is formed in the single crystalline layer 4. Although only asingle bipolar element is shown in the figure, bipolar elements areseparated by an element isolation silicon oxide film 6 formed in theelement isolation region. On the other hand, the CMOS elements 7 and 8are separated by an element isolation silicon oxide film 5 in theelement isolation region. The element isolation film 6 of the bipolarregion 9 is formed thicker than the element isolation film 5 of the CMOSregion 10 and therefore the height of the film 6 from the surface of thesubstrate is larger than that of the film 5. To explain morespecifically, the element isolation film 6 of the bipolar region 9differs in thickness from the element isolation film 5 of the CMOSregion 10, and therefore, their heights from the surface of thesubstrate differ.

A bipolar transistor has an emitter, base, collector, and collectorextraction layer which are formed in the single crystalline siliconlayer 4 of the bipolar region 9, and an emitter electrode, baseelectrode, and a collector electrode which are formed on the singlecrystalline silicon layer 4. A PMOS transistor of a CMOS transistorstructure has a P⁺ source/drain region formed in the single crystallinesilicon layer 3 of the CMOS region, a gate oxide film formed on thesingle crystalline silicon layer 3, and a gate electrode 7 formed on thegate oxide film. An NMOS transistor of the CMOS transistor structure hasan N⁺ source/drain region formed in the single crystalline silicon layer3 of the CMOS region, a gate oxide film formed on the single crystallinesilicon layer 3, and a gate electrode 8 formed on the gate oxide film.

As described in the above, in the conventional semiconductor device, theelement isolation film 6 of the bipolar region 9 is formed thicker thanthe element isolation film 5 of the CMOS region 10. Thus, the height ofthe element isolation film 6 from the surface of the substrate is largerthan the element isolation film 5. In other words, since the thicknessof the element isolation film 6 of the bipolar region differs inthickness from the element isolation film 5 of the CMOS region 10, theirheights from the surface of the substrate differ from each other. Thismakes it difficult to process a wiring layer formed over the bipolarregion 9 and the CMOS region 10. More specifically, in the manufacturingprocess of a semiconductor device having a plurality of SOI-Si layersdifferent in thickness on a single SOI substrate, since elementisolation is performed after a plurality of SOI-Si layers different inthickness are formed, the heights of the insulating films of the elementisolation region differ. Therefore, it is difficult to process a wiringlayer in a wiring formation step performed later. Furthermore, as aresult of the insulating films of the element isolation region differingin height, “out-of-focus” occurs in a lithography step later performed,rendering it difficult to perform a micro gate processing.

There is another publication (U.S. Pat. No. 5,294,823) besides theaforementioned publication (U.S. Pat. No. 5,212,397) in which aplurality of single crystalline semiconductor layers different inthickness which are formed on a buried insulating film, are integrallyformed into a single chip. However, in this conventional example, theelement isolation regions of the bipolar region and the CMOS region 10differ in height from the surface of a semiconductor substrate.Therefore, the same problems as in U.S. Pat. No. 5,212,397 resides alsoin U.S. Pat. No. 5,294,823.

BRIEF SUMMARY OF THE INVENTION

The present invention has been made under the aforementioned problems.An object of the present invention is to provide a semiconductor deviceand a method of manufacturing the semiconductor device in which theinsulating films of the element isolation region in a bipolar regionhave substantially the same height as that in the CMOS region, enablingmicro wiring processing easier.

The present invention is directed to a semi-conductor device having aplurality of semiconductor elements having a SOI-Si layer, which ischaracterized in that the element isolation films of a plurality ofsemiconductor elements have the substantially the same height from thesurface of the semiconductor substrate, that is, the surfaces of theelement isolation films form substantially the same plane. Furthermore,the present invention is characterized in that after element isolationregions are formed so as to form the same plane having the same heightfrom the surface of the semiconductor substrate a plurality of SOI-Sifilms (single crystalline silicon film) different in thickness areformed.

According to the present invention, element isolation insulating filmshave substantially the same height from a semiconductor substrate.Therefore, wiring processing can be performed easier. Furthermore,according to the present invention, it is possible to manufacture asemiconductor device having a plurality of semiconductor elements havingSOI-Si layers different in thickness without increasing the number ofsteps.

In a first aspect of the present invention, there is provided asemiconductor device comprising: a semiconductor substrate; a buriedinsulating film formed on the semiconductor substrate; a plurality ofsingle crystalline semiconductor layers, each having a semiconductorelement formed therein and being formed on the buried insulating film;and an element isolation region formed between adjacent singlecrystalline semiconductor layers, the element isolation insulating filmsformed in the element isolation region and having substantially the sameheight from the surface of the semiconductor substrate.

In the semiconductor device according to the first aspect of the presentinvention, at least one of the plurality of single crystallinesemiconductor layers may differ in thickness from other singlecrystalline semiconductor layers. In the semiconductor device, thesingle crystalline semiconductor layers may include a first singlecrystalline semiconductor layer having a MOS transistor formed thereinand a second single crystalline semiconductor layer having a bipolartransistor formed therein, the first and second single crystallinesemiconductor layers having substantially the same film thickness and athickness of the semiconductor layer lower than the gate electrode ofthe MOS transistor being lower than the film thickness of the secondsingle crystalline semiconductor layer. In the semiconductor device, inthe single crystalline semiconductor layers, a full depletion elementand a partially Depletion element may be formed.

In the semiconductor device according to the first aspect of the presentinvention, the single crystalline semiconductor layers may include afirst single crystalline semiconductor layer having a MOS transistorformed therein and a second single crystalline semiconductor layerhaving a bipolar transistor formed therein, the first and second singlecrystalline semiconductor layers having substantially the same filmthickness and a thickness of the semiconductor layer lower than the gateelectrode of the MOS transistor being lower than the film thickness ofthe second single crystalline semiconductor layer. In the semiconductordevice, in the single crystalline semiconductor layers, a full depletionelement and a partially Depletion element may be formed.

In the semiconductor device according to the first aspect of the presentinvention, in the single crystalline semiconductor layers, a fulldepletion element and a partially Depletion element may be formed.

In a second aspect of the present invention, there is provided asemiconductor device comprising: a semiconductor substrate having afirst region and a second region; a buried insulating film formed in thefirst region of the semiconductor substrate; at least one first singlecrystalline semiconductor layer having a semiconductor element formedtherein and formed in the buried insulating film and; at least onesecond single crystalline semiconductor layer formed in the secondregion and in contact with the semiconductor substrate; and an elementisolation region for isolating the single crystalline semiconductorlayers from each other, wherein all the element isolation insulatingfilms in the element isolation region have the same height from thesemiconductor substrate.

In the semiconductor device according to the second aspect of thepresent invention, the first single crystalline semiconductor layerformed in the first region may consist of a plurality of semiconductorlayers having a plurality of film thicknesses. In the semiconductordevice, a CMOS element may be formed in the first region and a bipolarelement may be formed in the second region. In the semiconductor device,a MOS transistor may be formed in a predetermined first singlecrystalline semiconductor layer of the first region; a bipolartransistor may be formed in a predetermined second single crystallinesemiconductor layer of the second region; the first and second singlecrystalline semiconductor layers have substantially the same height fromthe surface of the semiconductor substrate; and the thickness of thesemiconductor layer lower than the gate electrode of the MOS transistoris substantially the same as the thickness of a predetermined secondsingle crystalline semiconductor layer.

In the semiconductor device according to the second aspect of thepresent invention, a CMOS element may be formed in the first region anda bipolar element may be formed in the second region. In thesemi-conductor device, a MOS transistor may be formed in a predeterminedfirst single crystalline semiconductor layer of the first region; abipolar transistor may be formed in a predetermined second singlecrystalline semiconductor layer of the second region; the first andsecond single crystalline semiconductor layers have substantially thesame height from the surface of the semiconductor substrate; and thethickness of the semiconductor layer lower than the gate electrode ofthe MOS transistor is substantially the same as the thickness of apredetermined second single crystalline semiconductor layer.

In the semiconductor device according to the second aspect of thepresent invention, a MOS transistor may formed in a predetermined firstsingle crystalline semiconductor layer of the first region; a bipolartransistor may formed in a predetermined second single crystallinesemiconductor layer of the second region; the first and second singlecrystalline semiconductor layers have substantially the same height fromthe surface of the semiconductor substrate; and the thickness of thesemiconductor layer lower than the gate electrode of the MOS transistoris substantially the same as the thickness of a predetermined secondsingle crystalline semiconductor layer.

In a third aspect of the present invention, there is provided a methodof manufacturing a semiconductor device comprising the steps of: forminga semiconductor substrate by laminating a buried insulating film, asingle crystalline semiconductor layer, a first insulating filmsubsequently in this order; etching the first insulating film and thesingle crystalline semiconductor layer to form a plurality of laminatefilms consisting of the single crystalline semi-conductor layer and thefirst insulating film in the buried insulating film; forming a secondinsulating film on the semiconductor substrate so as to cover thelaminate films; flattening the second insulating film until the heightof the second insulating film from the semiconductor substrate becomesthe same as that of the first insulating film, thereby forming anelement isolation region; etching away the first insulating filmconstituting at least one laminate film to expose a surface of thesingle crystalline semiconductor layer under the first insulating film;and depositing the single crystalline semiconductor to a predetermineddepth on the exposed single crystalline semiconductor layer.

In a fourth aspect of the present invention, there is provided a methodof manufacturing a semiconductor device comprising the steps of: forminga semiconductor substrate by laminating a buried insulating film, asingle crystalline semiconductor element, a first insulating filmsubsequently in this order; etching the first insulating film and thesingle crystalline semiconductor layer to form a plurality of laminatefilms consisting of the single crystalline semi-conductor layer and thefirst insulating film on the buried insulating film; forming a secondinsulating film on the semiconductor substrate so as to cover thelaminate films; flattening the second insulating film until the heightof the second insulating film becomes substantially the same as that ofthe first insulating film to from an element isolation region; etchingaway at least one laminate film and simultaneously etching away theburied insulating film under the removed laminate film, thereby exposinga surface of the semiconductor substrate; etching the first insulatingfilm constituting at least one laminate film excluding the removedlaminate film, thereby exposing a surface of the single crystallinesemiconductor layer under the first insulating film; and depositing asingle crystalline semiconductor on the exposed single crystalsemiconductor layer to thicken the single crystalline semiconductorlayer, and simultaneously forming a single crystalline semiconductorlayer on an exposed surface of the semiconductor substrate, thicker thanthe single crystalline semiconductor layer formed on the buriedinsulating film.

In a fifth aspect of the present invention, there is provided a methodof manufacturing a semiconductor device comprising the steps of: forminga semiconductor substrate by laminating a buried insulating film, asingle crystalline semiconductor layer, a first insulating filmsubsequently in this order; etching the first insulating film and thesingle crystalline semiconductor layer to form a plurality of laminatefilms consisting of the single crystalline semi-conductor layer and thefirst insulating film on the buried insulating film; forming a secondinsulating film on the semiconductor substrate so as to cover thelaminate films; flattening the second insulating film until the heightof the second insulating film from the semiconductor surface becomessubstantially the same as that of the first insulating film to from anelement isolation region; etching away the first insulating filmconstituting at least one laminate film to expose a surface of thesingle crystalline semiconductor layer under the first insulating film;forming a MOS transistor on the single crystalline semiconductor layerwhose surface is exposed; etching away the first insulating film formedon a predetermined single crystalline semiconductor layer within thesingle crystalline semiconductor layer covered with the first insulatingfilm; depositing a single crystalline semiconductor on the singlecrystalline semiconductor layer having the MOS transistor formed thereinand on the single crystal semiconductor layer whose surface is exposed;and forming a bipolar transistor on a predetermined single crystallinesemiconductor layer whose surface is exposed.

In a sixth aspect of the present invention, there is provided a methodof manufacturing a semiconductor device comprising the steps of: forminga semiconductor substrate by laminating a buried insulating film, asingle crystalline semiconductor layer, and a first insulating filmsubsequently; etching the first insulating film and the singlecrystalline semi-conductor layer to form a plurality of laminate filmsconsisting of the single crystalline semiconductor layer and the firstinsulating film on the buried insulating film; forming a secondinsulating film on the semiconductor substrate so as to cover thelaminate films; flattening the second insulating film until the heightof the second insulating film from the semi-conductor surface becomessubstantially the same as that of the first insulating film to from anelement isolation region; etching away at least one laminate film andsimultaneously etching away the buried insulating film under the removedlaminate film to expose a surface of the underlying semiconductorsubstrate; depositing the single crystalline semi-conductor layer incontact with the surface of the exposed semiconductor substrate; etchingaway the first insulating film constituting at least one laminate filmexcluding the removed laminate film to expose a surface of the singlecrystalline semiconductor surface; forming a MOS transistor on theexposed single crystalline semiconductor layer; depositing a singlecrystalline semiconductor on the single crystalline semiconductor layerhaving the MOS transistor formed therein and simultaneously depositingon the single crystal semiconductor layer formed on the semiconductorsubstrate whose surface is exposed, thereby rendering the height of thesingle crystalline semiconductor layer having the MOS transistortherein, from the surface of the semiconductor substrate, substantiallythe same as that of the single crystalline semi-conductor layer formedon the semiconductor substrate whose surface is exposed; and depositingthe single crystalline semiconductor and forming a bipolar transistor onthe single crystalline semiconductor layer formed on the semiconductorsubstrate whose surface is exposed.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a cross-sectional view of a semi-conductor device according tothe present invention;

FIG. 2 is a cross-sectional view of a semi-conductor device according tothe present invention;

FIG. 3 is a cross-sectional view of a semi-conductor device according tothe present invention;

FIG. 4 is a cross-sectional view of a semi-conductor device according tothe present invention;

FIG. 5 is a cross-sectional view of a semi-conductor device according tothe present invention;

FIGS. 6A, 6B, and 6C are cross-sectional views of a semiconductor deviceof the present invention, showing manufacturing steps;

FIGS. 7A and 7B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 8A and 8B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 9A, 9B, and 9C are cross-sectional views of a semiconductor deviceof the present invention, showing manufacturing steps;

FIGS. 10A and 10B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 11A and 11B are cross-sectional views taken along the line 11A-11Aand 11B-11B of FIG. 10B;

FIGS. 12A, 12B, and 12C are cross-sectional views of a semiconductordevice of the present invention, showing-Manufacturing steps;

FIGS. 13A and 13B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 14A and 14B are cross-sectional views of portions taken along theline 14A-14A and 14B-14B of FIG. 13B;

FIGS. 15A and 15B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 16A and 16B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 17A and 17B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIG. 18 is a cross-sectional view of a semiconductor device according tothe present invention;

FIGS. 19A, 19B, and 19C are cross-sectional views of a semiconductordevice of the present invention, showing manufacturing steps;

FIGS. 20A, 20B, and 20C are cross-sectional views of a semiconductordevice of the present invention, showing manufacturing steps;

FIGS. 21A and 21B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIGS. 22A and 22B are cross-sectional views of a semiconductor device ofthe present invention, showing manufacturing steps;

FIG. 23 are cross-sectional views of a conventional semiconductordevice, showing manufacturing steps;

FIG. 24 are cross-sectional views of a conventional semiconductordevice, showing manufacturing steps; and

FIG. 25 is a cross-sectional view of a semiconductor device according tothe present invention.

DETAILED DESCRIPTION OF THE INVENTION

Now, various embodiments of the present invention will be explained withreference to the accompanying drawing.

In the first place, a first embodiment will be explained with referenceto FIG. 1. FIG. 1 is a cross-sectional view of a semiconductor devicehaving a plurality of single crystalline semiconductor layers differentin thickness.

On a silicon semiconductor substrate 11, a buried insulating film 12 of500 nm thick is formed which is, for example, made of a silicon oxide.On this structure, single crystalline silicon layers 14, 15 are formed.The film thickness of the single crystalline silicon layer 14 is, forexample, 50 nm. The film thickness of the single crystalline siliconlayer 15 is, for example, 100 nm. These single crystalline siliconlayers 14, 15 are isolated by an element isolation insulating film 13(made of e.g., silicon oxide film of abut 120 nm) of an elementisolation. On these single crystalline silicon layers 14, 15, a gateelectrode 17 of impurity-doped polysilicon is formed with a gateinsulating film 16 (such as silicon oxide film of e.g., 6 nm thick 9interposed between them. Furthermore, impurity diffusion regions 18, 19serving as source and drain regions are formed, respectively in thesingle crystalline silicon layers 14, 15. In FIG. 1, both of the gateinsulating films on the single crystalline layers 14, 15 have the samethickness of 6 nm. However, they may differ in thickness. If so,elements can be formed individually with the most desirable designs.

FIG. 1 only shows a transistor structure without a wiring structure.Usually, an LDD structure is employed in a miniaturized MOS transistor.In FIG. 1, a gate side wall insulating film and the impurity diffusionregion are not shown herein and the LDD structure is also omitted. As agate electrode structure, various structures may be employed including agate electrode structure formed of polysilicon/metal (silicide), a gateelectrode structure having an insulating film deposited further thereon,and a gate electrode formed of a metal. However, the structure of thegate electrode is also not shown. Furthermore, other structures, thatis, an impurity doped structure such as a well, formed in thesemiconductor substrate are not shown. The explanation just as in thecase of FIG. 1 will be made as to figures which will be explained later.

The feature of the present invention resides in that although aplurality of semiconductor elements having single crystalline siliconlayers different in thickness, are formed on the same semiconductorsubstrate, the insulating films of element isolating regions have thesame thicknesses. More specifically, since the height of the insulatingfilms from the surface of the substrate are equal, processing can bemade easily at the time the wiring layer is formed.

For example, if an FD (full depletion) element is formed in the thinsingle crystalline silicon layer 14 and a PD (partial depletion) elementis formed in a thick single crystalline silicon layer 15, it is possibleto form transistors different in threshold value on the same SOIsubstrate. More specifically, a semiconductor element having a thresholdof 0.2V can be formed in the single crystalline silicon layer 14 and asemiconductor element having a threshold of 0.4V in the singlecrystalline silicon layer 15. Therefore, if the circuit which has to beoperated with a low power consumption by reducing a power source voltageto about 1.2V, is formed in the single crystalline silicon layer 14, andthe circuit which is operated at a high speed by increasing the powersource voltage to 3.3V, is formed in the single crystalline siliconlayer 15, it is possible to manufacture a high-speed semiconductordevice with a power consumption lower than a conventional semiconductordevice. The advantages of the semiconductor device of this type is dueto the structure in which the FD element which is low in thresholdvoltage, excellent in cut-off characteristics, that is, low in leakcurrent, and the PD element excellent in power-source resistance areformed in the same SOI substrate.

If the present invention is used, a circuit formed of the PD elementhaving a polysilicon gate (gate length: 0.25 μm, SOI film thickness: 80nm, an impurity concentration: 7×10¹⁷ cm⁻³) and a circuit formed of theFD element having a metal gate (SOI film thickness: 30 nm, impurityconcentration: 1×10¹⁷ cm⁻³) are easily formed on the same semiconductorsubstrate without changing a circuit design.

In the next step, if two types of SOI films of 100 μm and 50 μm thickare further formed with an impurity concentration of 5×10¹⁷ cm⁻³ and aPD/FD element is formed of a polysilicon gate, the step of changing animpurity concentration can be eliminated.

It is therefore possible to easily form a circuit different in design byusing the present invention.

Furthermore, if an NMOS element is formed in the thin single crystallinesilicon layer 14 and a PMOS element is formed in the thick singlecrystalline silicon layer 15, it is possible to realize a CMOS circuitwhile preventing kink characteristics of the NMOS element. In this case,both the NMOS element and the PMOS element may be formed of the PDelement.

Furthermore, a MOS transistor and a bipolar transistor may be integratedin the same SOI substrate.

FIG. 2, which is a modified example of the first embodiment shown inFIG. 1, shows a cross-sectional view of a semiconductor device having aplurality of single crystalline semiconductor layers different inthickness.

Now, the semiconductor device shown in FIG. 2 will be explained. On asilicon semiconductor substrate 11, a buried insulating film 12 isformed which is a silicon oxide film of, e.g., 500 nm thick. On theburied insulating film 12, single crystalline silicon layer 14, 15 areformed, which are isolated by an element, isolation insulating film 13of, e.g., 120 nm thick. The single crystalline silicon layers 14, 15 are50 nm and 100 nm in thickness, respectively. On the single crystallinesilicon layer 14, a impurity-doped polysilicon gate electrode 17 isformed with a gate insulating film 16 of e.g., 6 nm thick interposedbetween them. In the single crystalline silicon layer 14, an impuritydiffusion region 18 serving as a source/drain region is formed. On theother hand, a base electrode 110 formed of polysilicon doped withimpurity is formed on the single crystalline silicon layer 15. At theside of the base electrode 110, a side-wall insulating film 111 isformed. In the single crystalline silicon layer 15, impurity diffusionregions 112, 113 serving as an emitter region and a collector region areformed, respectively wiring layers are omitted herein in the same as inFIG. 1.

In the case of FIG. 2, even if the elements having silicon layersdifferent in thickness are formed on the same substrate, the insulatingfilms of the element isolation regions are almost the same in thickness.More specifically, since the heights of the insulating films from thesurface are equal, processing can be made easily in a wiring formationstep performed later.

As an application example of the semiconductor device of this type, aMOS transistor, which is an FD (full depletion) element or a PD (partialdepletion) element, is formed in thin single crystalline silicon layer14 and a lateral bipolar element is formed in the thick singlecrystalline silicon layer 15. If the circuit which has to be operatedwith a low power consumption, is formed in the single crystallinesilicon layer 14, and the bipolar element requiring high frequencycharacteristics is formed in the single crystalline silicon layer 15, itis possible to manufacture a high-speed semiconductor device which canbe operated with a power consumption lower than a conventionalsemiconductor device. This is because if a MOSFET is formed in the thinsingle crystalline silicon layer (SOI-Si layer), a semiconductor elementhaving a low threshold voltage and excellent cut-off characteristics isobtained, whereas if the bipolar element is formed in the thick singlecrystalline silicon layer (SOI-Si) layer, a bipolar element excellent inhigh-frequency characteristics is obtained.

FIG. 25 is a cross-sectional view of a semi-conductor device accordingto the present invention.

In the semiconductor device shown in FIG. 25, single crystalline siliconlayers 14, 15 have substantially the same thickness, e.g., 100 nm. Otherportions or parts are identical with those of the semiconductor deviceshown in FIG. 2, and the description is omitted. In this case, it may beunavoidable that the power consumption is increased and the operationspeed is lowered as compared with the semiconductor device shown in FIG.2.

Now, a second embodiment will be explained with reference to FIG. 3.

FIG. 3 is a cross-sectional view of a semiconductor device having aplurality of single crystalline semiconductor layers different inthickness.

On a silicon semiconductor substrate 31, a buried insulating film 32such as a silicon oxide film of, e.g., 500 nm thick is formed. On theburied insulating film 32, single crystalline layers 34, 35 are formedwhich are isolated by an element isolation insulating film 33 of 120 nmthick. The single crystalline silicon layers 34, 35 are 50 nm and 100 nmin thickness, respectively. Laminate gate electrode 37, 38 and a gateelectrode 39 doped with impurities are formed on the single crystallinesilicon layers 34, 35 with a gate insulating film 36 of e.g., 6 nm thickinterposed between them. More specifically, a polysilicon electrodelayer 37 of, e.g., 50 nm thick and a polysilicon electrode layer 38 ofe.g., 200 nm thick are laminated on the single crystalline silicon layer34. On the single crystalline silicon layer 35, a polysilicon electrode39 of e.g., 200 nm thick is formed.

Note that, the polysilicon laminate gate electrodes 37 and 38 are notnecessarily laminated and may be formed of a polysilicon single layerhaving a film thickness of about 250 nm. Furthermore, the singlecrystalline silicon layers 34, 35 may have impurity diffusion regions310, 311 formed therein, which serve as source and drain regions.

FIG. 3 shows only a transistor structure without the wiring layerstructure in the same as in FIGS. 1 and 2.

As explained in the foregoing, even though the semiconductor elementshaving different single crystalline silicon layers are formed on thesame SOI substrate, the insulating films of the element isolationregions have the same thickness in this embodiment. Since the heights ofthe insulating films from the substrate are equal, processing can bemade easily in a wiring formation step performed later. In addition, theheights of the polysilicon gate electrodes from the surface of thesubstrate are equal. Since the heights of the polysilicon electrodesfrom the surface of the substrate are equal, the thin single crystallinesilicon layer 34 and the thick single crystalline silicon layer 35 havethe same depth of focus in a lithographic step for the gate electroderequiring the microprocessing of the highest level. Therefore, the moreminiaturized and more accurate processing can be performed.

The same semiconductor elements formed on the thin single crystallinesilicon layer 34 and the thick single crystalline silicon layer 35 arethe same as in the first embodiment.

FIG. 4 is a modified example of the second embodiment shown in FIG. 3,showing a cross-sectional view of a semiconductor device having aplurality of single crystalline semiconductor layers different inthickness.

The semiconductor device shown in FIG. 4 has a plurality of singlecrystalline silicon layers different in thickness, as the same as inFIG. 3. The semiconductor device is characterized in that a two-layeredgate electrode is formed on the single crystalline silicon layer 34 withan insulating film interposed between them. More specifically, on thesingle crystalline silicon layer 34, a tunnel oxide film 312 such as anitrogen-containing silicon oxide film of 8 nm thick is formed. On thetunnel oxide film 312, a polysilicon floating gate electrode 37 servingas a first gate electrode, an interlayer insulating film 313 ofpolysilicon oxide film of 12 nm thick, and a polysilicon control gateelectrode 38 serving as a second gate electrode, are laminated. On theother hand, on the single crystalline silicon layer 35, a gateinsulating film 314 such as a silicon oxide film and a gate electrode 39such as polysilicon are formed.

The interlayer insulating film 313 and the gate insulating film formedof silicon oxide film are formed simultaneously. Similarly, the secondgate electrode 38 and the gate electrode 39 are formed simultaneously

As described in the above, in this embodiment, it is possible to form anon-volatile memory cell on the thin single crystalline silicon layer 34and form a logic circuit on the thick single crystalline silicon layer35. In this case, the same advantages as in FIG. 3 can be obtained.

Now, a third embodiment will be explained with reference to FIG. 5.

FIG. 5 is a cross-sectional view of a semiconductor device having aplurality of single crystalline semiconductor layers different inthickness.

FIG. 5 shows the features of the present invention including a buriedinsulating film, an element isolation insulating film (element isolationregion), and the structure of the surface of the single crystallinesilicon layer on which a semiconductor element is to be formed; however,a gate electrode and the shape of a impurity diffusion region are notshown.

In FIG. 5, on a silicon semiconductor substrate 51, a buried insulatingfilm 52 such as a silicon oxide film of e.g., 500 nm, is formed. On theburied insulating film 52, single crystalline silicon layers 54, 55 areformed, which are isolated by element isolation insulating films 53 ofe.g., 120 nm thick. These single crystalline silicon layers 54, 55 are50 nm and 100 nm in thickness, respectively. Furthermore, a part of theburied insulating film 52 is removed by etching using the elementisolation insulating film 53 as a mask. The surface of the siliconsemiconductor substrate 51 is exposed in this part. The siliconsemiconductor substrate 51 is joined to the single crystalline siliconlayer 56 so as to form an indiscrete silicon crystal in this part.

The element isolation insulating films 53 maintain almost the sameheight from the surface of the substrate over the entire semiconductorsubstrate. The single crystalline silicon layers 54, 55 and 56 havealmost the same height. Since the number of processing errors due to“out of focus” decreases, microprocessing can be easily performed in alithographic step for isolating elements and processing a gate.Furthermore, since the wiring layer formed in a later step has a steppedportion having a small difference in height, fine processing of thewiring can be performed easily. As a result, it is possible to preventbreakage of the wiring and occurrence of defects such as short-circuit,improving the yield of the semiconductor device.

In this embodiment, three types of semiconductor elements can beintegrated. More specifically, a thin SOI thin-film element, amedium-thick SOI thin-film element, and a bulk element can be integratedon a single SOI substrate. The semiconductor device of this embodimentdiffers from those shown in FIG. 1 to FIG. 4 in that the bulk elementcan be integrated.

Thin SOI thin-film element and the medium thick SOI thin-film elementcan be integrated in the same manner as in FIG. 1 to FIG. 4. Theadvantages obtained by integrating the bulk element with the SOIelements on the same SOI substrate are as follow: A memory element suchas DRAM (the fluctuation of a substrate voltage is desirably low and athreshold voltage is relatively high), a vertical bipolar element inwhich current flows relatively to the depth of a silicon semiconductorsubstrate, an nMOS transistor which easily causes deterioration ofcharacteristics due to impact-ionization such as kink, high breakdownvoltage semiconductor element which is used in a region to which arelatively high power voltage is applied, and an analog element whichrequires the linearity of the element characteristics, are formed in abulk silicon. In addition, these semiconductor elements can be formed onthe same SOI substrate.

Now, a fourth embodiment will be explained with reference to FIGS. 6A,6B, and 6C and FIGS. 7A and 7B.

FIGS. 6A, 6B, and 6C and FIGS. 7A and 7B are cross-sectional viewsshowing manufacturing steps of a semiconductor device (shown in FIG. 1)having a plurality of single crystalline semiconductor layers differentin thickness.

In the first place, on the silicon semiconductor substrate 61, a buriedinsulating film 62 formed of a silicon oxide film of 500 nm thick and asingle crystalline silicon layer 63 of 50 nm thick are laminated in thisorder to form a SOI substrate (FIG. 6A). Subsequently, the surface ofthe single crystalline silicon layer 63 is oxidized by heating thesemiconductor substrate 61 at 900° C. in an oxygen atmosphere. As aresult, a gate insulating film 64 formed of a silicon oxide film of 6 nmthick, is obtained. Subsequently, a silicon nitride film (SiN) 65 ofabout 150 nm thick is deposited on the resultant structure by an LPCVD(low Pressure Chemical Vapor Deposition) method. Thereafter, a siliconoxide film (SiO₂) 66 of about 100 nm thick is deposited by a CVD method.If necessary, a heat treatment is applied to the silicon oxide film 66to densify and cure it. After that, photoresist is allowed to remainonly in the element formation region by a photolithographic method.Using the photoresist as a mask, a laminate body consisting of thesilicon oxide film 66, the silicon nitride film 65, and the gateinsulating film, is patterned by a RIE method, followed by removing thephotoresist. Subsequently, using the silicon oxide film 66 as a mask,the single crystalline silicon layer 63 is etched by a RIE method (FIG.6B). Thereafter, an oxidation treatment is applied to the surface of thesemiconductor substrate (not shown in the figure).

Then, a silicon oxide film 67 of 500 nm thick is deposited by an LPCVDmethod (FIG. 6C). Thereafter, the silicon oxide films 66, 67 arepolished by the CMP method to remove the silicon oxide film 66 until thesurface of the silicon oxide film 67 and the surface of the siliconnitride film 65 are in the same plane. At this time, the surface of thesilicon nitride film 65 may be slightly removed. In the elementisolation region, a silicon oxide film of about 120 nm thick is formedas the element isolation insulating film 67 almost uniformly over theentire surface of the substrate by a CMP processing. Thereafter, aphotolithographic step is performed. A patterned photoresist is formedhaving an opening only at a portion at which the single crystallinesilicon layer 63 is to be formed thick. Using the patterned photoresistas a mask, the silicon nitride film 65 is etched with hot phosphoricacid and the silicon oxide film (gate insulating film) 64 is etched awaywith hydrofluoric acid. After that, the photoresist is removed to allowpart of the surface of the single crystalline silicon layer 63 to expose(FIG. 7A).

Subsequently, a single crystalline silicon layer 68 of about 50 nm thickis selectively deposited on the exposed surface of the singlecrystalline silicon layer 63, by the LPCVD method. Then, the siliconnitride film 65 is etched away with hot phosphoric acid, and then, theinsulating film 64 formed of a silicon oxide film is etched away withdiluted hydrofluoric acid (FIG. 7B).

In this embodiment, it is possible to attain a semiconductor deviceaccording to the present invention, having single crystalline siliconlayers different in thickness formed on the same SOI substrate andhaving insulating films of the element isolation regions equal inthickness (as shown in FIG. 7B). After that, if the SOI substrate isprocessed as shown in FIG. 7B, followed by performing generally CMOSmanufacturing steps, it is possible to form a semiconductor device shownin FIG. 1. Furthermore, if a CMOS step and a lateral bipolar step areapplied to the resultant structure, the semiconductor device shown inFIG. 2 can be obtained.

The method of forming single crystalline silicon layers different inthickness can be modified in various ways. In the aforementionedmanufacturing method, the single crystalline silicon layer having adesired thickness can be obtained by using a selective silicon epitaxialdeposition method. However, the same structure may be obtained byepitaxially growing silicon to a thickness higher than the thickness ofthe element isolation insulating film 67 to overfill silicon andremoving the single crystalline silicon from an unnecessary portion by aCMP technique. The advantages of this case are: the thickness of thesilicon layer can be easily controlled; and a problem of a facet whichtends to occur during the epitaxial deposition can be overcome.

As a method as effective as the aforementioned method, the method may beemployed which includes depositing amorphous silicon over the entiresurface of the substrate, annealing the resultant structure to allowsolid-phase growth using a part in contact with the single silicon layeras a seed, and removing an unnecessary silicon by a CMP method.

Conversely, a method of thinning the single crystalline silicon layerincludes thermally oxidizing the surface of the single crystallinesilicon layer after the step shown in FIG. 7A, thereby oxidizing theexposed surface to thin the oxidized portion of the single crystallinesilicon layer. As a further simpler method, the exposed singlecrystalline silicon layer alone may be thinned by a CDE (Chemical DryEtching) method and RIE (Reactive Ion Etching) method. If necessary, anoxidation process is performed, thereby reducing an etching damage.

Subsequently, a fifth embodiment will be explained with reference toFIGS. 8A and 8B.

FIGS. 8A and 8B are cross-sectional views showing manufacturing steps ofa semiconductor device having a plurality of single crystallinesemiconductor layers different in thickness. The semiconductor device ofthis embodiment is characterized in that the single crystallinesemiconductor layers differ in thickness and the gate oxide films formedthereon further differ in thickness.

The method of manufacturing the semiconductor device is the same as inthe fourth embodiment up to the step shown in FIG. 7A. After that, asingle crystalline silicon layer 68 of about 50 nm thick is selectivelydeposited on the surface of the single crystalline silicon layer by aLPCVD method. Subsequently, a silicon nitride film 65 is etched with hotphosphoric acid (FIG. 8A). Thereafter, the surface of a singlecrystalline silicon layer 63 and the surface of a single crystallinesilicon layer 68 are oxidized by a thermal oxidation method to a depthof about 4 nm. At this time, on the thick single crystalline siliconlayer formed by depositing the single crystalline silicon layer 68formed on the thick single crystalline silicon layer 63, a gate oxidefilm 69 such as a silicon oxide film of 4 nm thick is formed. However,on the thin single crystal silicon layer 63, consisting of the singlecrystal silicon layer 63 alone, a silicon oxide film of 6 nm thick hasbeen formed before the oxidation (see FIG. 8A). Therefore, a gateinsulating film 610 formed of a silicon oxide film of about 8 nm thickis formed (FIG. 8B). Thereafter, a polysilicon layer serving as a gateelectrode is deposited. It is therefore possible to integratesemiconductor elements each having the single crystalline silicon layerand the gate insulating film different in thickness on the same SOIsubstrate. The element isolation insulating films in the elementisolation region have the same height.

Now, a sixth embodiment will be explained with reference to FIGS. 9A,9B, and 9C to FIGS. 11A and 11B.

FIGS. 9A, 9B, and 9C and FIGS. 10A and 10B are cross sectional viewsshowing manufacturing steps of a semiconductor device shown in FIG. 3 inwhich the insulating films in the element isolation region have almostthe same thickness even though the semiconductor elements having singlecrystalline silicon layers different in thickness are formed on the sameSOI substrate. The semiconductor device is characterized in that a laterwiring layer formation process can be easily performed since the elementisolation insulating films have the same height, and in that the gateelectrodes have the same height.

The process is the same as shown in FIG. 6A up to the process in which aSOI substrate is prepared by laminating a buried insulating film 82formed of a silicon oxide film of 500 nm and a single crystallinesilicon layer 83 of 50 nm thick, on a silicon semiconductor substrate81.

Then, the single crystalline silicon layer 83 is subjected to a heattreatment in an oxygen atmosphere at 900° C. to oxidize the surfacethereof. As a result, a gate insulating film 84, which is a siliconoxide film of 6 nm thick is formed. Subsequently, a polysilicon film 85of 50 nm thick and a silicon nitride film (SiN) 86 are successivelydeposited by a LPCVD. Furthermore, a silicon oxide film (SiO₂) 87 of 100nm thick is deposited by a CVD method on the resultant structure. Ifnecessary, the silicon oxide film 87 is densified to cure by applying aheat treatment.

Subsequently, a patterned photoresist (not shown), which is designed soas to leave the photoresist only at an element formation region by aphotolithographic method, is formed on the silicon oxide film 87. Usingthe photoresist as a mask, the silicon oxide film 87, silicon nitridefilm 86, polysilicon film 85, and silicon oxide film 84 are etched awayby a RIE method. Thereafter, the photoresist is removed (FIG. 9A).

Then, using the silicon oxide film 87 as a mask, the single crystallinesilicon layer 83 is etched away by a RIE method. Thereafter, oxidationis applied to the resultant structure (not shown in the figure).Subsequently, a silicon oxide film 88 of 500 nm thick is deposited so asto cover a laminate body consisting of the silicon oxide film 87, thesilicon nitride film 86, the polysilicon film 85, and the silicon oxidefilm 84 (FIG. 9B).

Next, the surface of the silicon oxide film 88 is polished by a CMPmethod until the surface of the silicon nitride film 86 is exposed,thereby removing the silicon oxide film 87. At this time, the surface ofthe silicon nitride film 86 is slightly removed. By the polishingprocess, the silicon oxide film 88 of about 120 μm thick is formedalmost uniformly over the substrate, as an element isolation insulatingfilm, in the element isolation region.

Thereafter, a photoresist (not shown) having an opening only at a regionat which the single crystalline layer is to be formed thick, is formedby a photolithographic step on the silicon nitride film 86 and thesilicon oxide film 88. Using the photoresist as a mask, the siliconnitride film 86 within an opening is etched away with hot phosphoricacid, the polysilicon film 85 is etched away by a CDE method, thesilicon oxide film 84 is etched away with diluted hydrofluoric acid, andfurther the photoresist is removed. In this manner, the surface of thesingle crystal silicon layer 83 on which the opening of the photoresistis formed, is exposed.

Then, the single crystalline silicon layer 89 of 50 nm thick isselectively deposited by a LPCVD method on the surface of only theexposed single crystalline silicon layer 83. At this time, the height ofthe polysilicon film 85 has almost the same as that of the singlecrystalline silicon layer 89. Various methods explained in the fourthembodiment may be used herein. Subsequently, an insulating film 810,which is a silicon oxide film of 4 nm thick, is formed by a thermaloxidation step. Subsequently, a silicon nitride film 86 covering thepolysilicon film 85 is etched away with hot phosphoric acid (FIG. 10A).

Subsequently, a polysilicon gate electrode 811 of 100 nm thick isdeposited by a LPCVD method. The resultant structure is furthersubjected to a gate processing to obtain a gate structure shown in FIG.10B.

Cross-sectional views of a portion taken along the line 11A-A11 and aportion taken along the line 11B-11B of FIG. 10B are shown in FIGS. 11Aand 11B. Although detailed explanation is omitted, the gate electrode ofthe portion taken along the line 11A-11A is formed of a first gateelectrode 85 and a second gate electrode 811 directly mounted on thegate electrode 85. The gate electrode of the portion taken along theline 11B-11B is constituted of the second gate electrode 811 alone. Bothgate electrodes have almost the same height from the surface of thesemiconductor substrate 81.

As shown in FIG. 10B, it is possible to attain a semiconductor device ofthe second embodiment having the following advantages: singlecrystalline silicon layers different in thickness can be formed on thesame SOI substrate; the gate electrodes formed on individual singlecrystalline silicon layers may have the same height from the surface ofthe substrate; the thickness of gate oxide films on the individualsingle crystalline silicon layers can be changed independently of eachother; and the element isolation insulating films in the elementisolation region may have almost the same thickness.

A further simpler method can be employed in order to form the gateelectrodes at the same height to prevent the “out-of-focus” in thephotolithographic step, improving the yield and reliability of a wiringformation step for wiring to be formed over the gate electrodes. Morespecifically, the fact that the difference in height of the singlecrystalline silicon layers affects the difference in height of thepolysilicon films from the surface of the substrate becomes apparent forthe first time after the structure shown in FIG. 6A is formed, the gateoxidation step is performed, and the polysilicon film is deposited.Therefore, the uneven polysilicon film may be polished flat by a CMPmethod. In the structure of FIG. 10B, a part of the gate electrode mayhave a multi-layered polysilicon structure. However, all gate electrodesformed by this method have a single-layered structure. As described, itis possible to control the height of the polysilicon film at the samelevel by performing CMP. This is because the heights of the insulatingfilms in the element isolation region are equal even though the singlecrystalline silicon layers differ in thickness. If the heights of theinsulating films are not the same, this method is not applicable since apart of the element isolation region is cut off.

Now, a seventh embodiment will be explained with reference to FIGS. 12A,12B, and 12C and FIGS. 14A and 14B.

FIGS. 12A, 12B, 12C and FIGS. 13A and 13B are cross-sectional views of asemiconductor device having a structure (shown in FIG. 4) consisting ofa plurality of single crystalline silicon layers different in thicknessand two-layered gate electrodes formed on the single crystalline siliconlayers with an insulating film interposed between them.

In the first place, a SOI substrate is prepared by laminating a buriedinsulating film 92 of a silicon oxide film of 500 nm thick and a singlecrystalline silicon layer 93 of 50 nm thick on a silicon semiconductorsubstrate 91. Subsequently, the resultant structure is subjected to aheat treatment at 900° C. to oxidize the surface of the singlecrystalline silicon layer 93 to form a silicon oxide film 94 of 8 nmthick, followed by subjecting to a nitrification treatment.

Then, a polysilicon film 95 of 50 nm thick and a silicon nitride film 96of 100 nm thick are successively deposited by a LPCVD method.Furthermore, a silicon oxide film 97 of 100 nm thick is deposited by aCVD method. If necessary, the silicon oxide film 97 is densified to cureby a heat treatment. Thereafter, photoresist (not shown) is formedhaving an opening portion at an element formation region by aphotolithographic method.

Using the photoresist as a mask, the silicon oxide film 97, the siliconnitride film 96, the polysilicon film 95, and the silicon oxide film 94are etched away by a RIE method. Thereafter, the photoresist is removed(FIG. 12A).

Then, using the silicon oxide film 97 as a mask, the single crystallinesilicon layer 93 is etched away by a RIE method. Thereafter, theresultant structure is subjected to an oxidation process (not shown inthe figure). Subsequently, a silicon oxide film 98 of 500 nm thick isdeposited by a LPCVD method (FIG. 12B). Then, the surface of the siliconoxide films 97, 98 are polished by a CMP method. At that time, thesurface of the silicon nitride film 96 is slightly removed. In this way,an element isolation insulating film 98 formed of a silicon insulatingfilm is formed almost uniformly with a thickness of about 120 nm overthe entire surface of the silicon substrate.

Thereafter, a photoresist is formed having an opening portion which isformed so as to include the region for forming a thick singlecrystalline silicon layer in a later step. Using the photoresist as amask, the silicon nitride film 96 is etched away with hot phosphoricacid, the polysilicon film 95 by a CDE method, and the silicon oxidefilm 94 with diluted hydrofluoric acid. Thereafter, the photoresist isremoved to allow the surface of the silicon oxide film 94 to partlyexpose. Subsequently, a polysilicon layer 99 of about 50 nm thick isselectively formed on only the surface of the single crystalline siliconlayer by a LPCVD method (FIG. 12C). At this time, the height of thepolysilicon film 95 from the surface of the substrate is almost equal tothe height of the polysilicon layer 99 from the surface. Note thatvarious methods explained in the fourth embodiment can be employedherein.

Subsequently, the silicon nitride film 96 is etched away with hotphosphoric acid. Then, an oxide film 910 of 12 nm thick is formed on thesilicon oxide film 98 by a thermal oxidation step. At that time, apolysilicon oxide film 911 is formed also on the polysilicon film 95(FIG. 13A). Thereafter, a polysilicon film 912 of 100 nm thick isdeposited by a LPCVD method and gate processing is applied to theresultant structure to thereby obtain a structure of FIG. 13B.

Other cross-sectional views of the structure shown in FIG. 13B are shownin FIGS. 14A and 14B. In FIG. 14A, on the single crystalline siliconlayer 93, a tunnel oxide film 94, a floating gate 95, a gate insulatingfilm 911, and a control gate 912 are laminated to form a nonvolatilememory. Furthermore, in FIG. 14B, on the single crystalline siliconlayer 99, a gate oxide film 910 and a gate electrode 912 are laminatedto form a general logic circuit, which is the same structure as shown inthe second embodiment.

As shown in FIG. 10B, single crystalline silicon layers different inthickness are formed on the same SOI substrate; the heights of the gateelectrodes from the surface of the substrate are present at the samelevel; the thickness of the gate oxide film can be changed dependingupon the film thickness of each of the single crystalline siliconlayers; and the insulating films in the element isolation region havesubstantially the same thickness; in the same as in the sixthembodiment.

Next, an eight embodiment will be explained with reference to FIGS. 15Aand 15B to FIGS. 17A and 17B.

FIGS. 15A and 15B to FIGS. 17A and 17B are cross-sectional views of asemiconductor device shown in FIG. 5 having a plurality of singlecrystalline semiconductor layers different in thickness. In FIG. 5, thestructural features of the present invention are shown which include theburied insulating film, the element isolation insulating film (elementisolation region), and the surface of the single crystalline siliconlayer on which a semiconductor element is to be formed whereas othersemiconductor structures including the gate electrode and the shape ofthe impurity diffusion region are not shown.

In the first place, a SOI substrate is prepared which is formed bylaminating a buried insulating film 122 of a silicon oxide film of 500nm thick and a single crystalline silicon layer 123 of 50 nm thick, on asilicon semiconductor substrate 121. Subsequently, a silicon oxide film124 of 6 nm thick is formed by subjecting the semiconductor substrate toa heat treatment at 900° C. to oxidize the surface of the singlecrystalline silicon layer 123. Subsequently, the silicon nitride film125 of about 220 nm thick is deposited by a LPCVD method. Furthermore, asilicon oxide film 126 of 100 nm thick is deposited by a CVD method. Ifnecessary, the silicon oxide film 126 may be densified to cure byapplying a heat treatment. Subsequently, the photoresist having anopening portion corresponding to the element formation region, is formedby a photolithographic method.

Using the photoresist as a mask, the silicon oxide film 126, the siliconnitride film 125, and the silicon oxide film 124 are etched away by aRIE method. Thereafter, the photoresist is removed and then the singlecrystalline silicon layer 123 is etched away by a RIE method using thesilicon oxide film 126 as a mask. Thereafter, the oxidation processingis performed (not shown in the figure).

Subsequently, a silicon nitride film 127 of 500 nm thick is deposited soas to cover the silicon oxide film 126, the silicon nitride film 125,and the silicon oxide film 124 (FIG. 15A). Thereafter, the silicon oxidefilm 126 and the surface portion of the silicon oxide film 127 areremoved by a CMP method. At this time, the surface of the siliconnitride film 125 is slightly removed. At this time, in the elementisolation region, element isolation insulating film 127 of a siliconoxide film of about 190 nm thick are formed almost uniformly over theentire surface of a silicon wafer (FIG. 15B).

Thereafter, only the silicon oxide film 127 is etched away by a RIEmethod to the depth of about 70 nm to form a groove. Subsequently, thepolysilicon film 128 of about 100 nm thick is deposited by a LPCVDmethod. Polysilicon except inside the groove is removed by a CMP method.Note that a laminate body of a silicon nitride film and a polysiliconfilm is used in place of the polysilicon film.

Thereafter, a photoresist 129 is formed having an opening portionsurrounding a region in which a bulk semiconductor element is to beformed. Using the photoresist 129 and the polysilicon 128 as a mask, thenitride silicon film 125 is etched away with hot phosphoric acid, thesilicon oxide film 124 with a dilute hydrofluoric acid, the singlecrystalline silicon layer 123 by a RIE method, and a buried insulatingfilm 122 by a RIE method. Subsequently, the photoresist 129 is removedto allow the surface of the silicon semiconductor substrate to partlyexpose (FIG. 16B). Note that the single crystalline silicon layer 123has to be carefully etched so as not to completely each away thepolysilicon film 128. Thereafter, a photoresist (not shown) having anopening portion which includes a region at which a single crystallinesilicon layer to be formed thick, is formed by a photolithographic step.Using the photoresist as a mask, the silicon nitride film 125 is etchedaway with hot phosphoric acid, and the silicon oxide film 124 withdiluted hydrofluoric acid. Thereafter, the photoresist is removed topartially expose the surface of the single crystalline silicon layer123. Subsequently, an amorphous silicon film 1211 of 1 μm thick isdeposited by a LPCVD method (FIG. 17A).

In this case, the recess 1210 in the polysilicon film 128 of FIG. 16Brarely have a negative effect on the later steps. Conversely, since therange of depositing the amorphous silicon film 1211 is enlarged, thecoverage with the amorphous silicon film 1211 can be effectively made.The shape of the recess 1210 does not remain as shown later. Theamorphous silicon film 1211 can be crystallized into a singlecrystalline by using a portion in contact with a single crystallinesilicon as a seed.

It is difficult for the amorphous silicon film to be converted into asingle crystal on the silicon nitride film 125 and the polysilicon film128 and usually changed into a polysilicon. The portion changed intopolysilicon and the polysilicon film 128 such as a thin-film polysiliconused as a mask are simultaneously removed by a CMP method and then thesingle-crystalline portions 1213 and 1214 are flattened. The remainingnitride silicon film 125 is etched away with hot phosphoric acid and thesilicon oxide film 124 with diluted hydrofluoric acid. As a result, thestructure of the SOI substrate shown in FIG. 17B can be obtained. Thisstructure is the same as that shown in FIG. 5.

In this embodiment, the silicon surface of the bulk semiconductorelement is lifted up to the level of the element isolation insulatingfilm by depositing amorphous silicon, forming into a single crystal andapplying CMP thereto. However, similar effects can be obtained if aselective epitaxial deposition technique is used. In this case, theheight of the silicon layer in a bulk semiconductor element region islower than that of the element isolation insulating film. However,compared to the case where the surface of the silicon layer is notlifted up, the “out-of-focus” of the photolithographic step can beimproved and the yield and reliability of the wiring formation step(forming wiring above) can be greatly improved. In addition, the stepscan be simplified.

When only the same thickness of the single crystalline semiconductorlayers is required as the single crystalline semiconductor layers, anamorphous silicon is deposited on the structure shown in FIG. 16B andallowed to change into a single-crystalline structure.

The semiconductors explained in the aforementioned embodiments are thosein which semiconductor elements having a plurality of single crystallinesemiconductor layers (SOI-Si layer) different in thickness areintegrated and the element isolation insulating films havingsubstantially the same height. In the following embodiments, asemiconductor and a method of manufacturing the semiconductor will beexplained which is characterized in that a single crystallinesemi-conductor layer having a MOS transistor formed therein hassubstantially the same height from the surface of the semiconductorsubstrate as that of a single crystalline semiconductor layer having abipolar transistor from the surface.

Now, a ninth embodiment will be explained with reference to FIG. 18.

FIG. 18 is a cross-sectional view of a silicon semiconductor which has aregion having a MOS transistor formed therein and a region having abipolar transistor formed therein. On a silicon semiconductor substrate(SOI substrate) 131, a buried insulating film 132, which is a siliconoxide film of about 500 nm thick, is deposited. On the resultantstructure, a plurality of element regions are formed while beingisolated by element isolation insulating films 133. In the elementregion, single crystalline silicon layers 134, 1311 are formed. Thesingle crystalline silicon layers 134, 1311 have a film thickness of 100nm. On the single crystalline silicon layer 134, a gate electrode 136 ofimpurity-doped polysilicon is formed with a gate oxide film 135 of 6 nmthick interposed between them. The gate electrode 136 is covered with asilicon nitride (SiN) film 137. At the sides of the gate electrode 136and the silicon nitride film 137, a gate side wall 138 is formed of asilicon oxide film, silicon nitride film, or a laminated film consistingof the silicon nitride film and the silicon oxide film. A large amountof impurities are doped into both sides of the gate side wall 138. Asingle crystalline silicon semiconductor layer 139 is formed higher thanthe gate oxide film 135, that is, about 100 nm thick on the singlecrystalline silicon semiconductor layer 134. The single crystallinesilicon semiconductor layer 139 forms a source/drain region of an MOStransistor. The source/drain region is formed also in the singlecrystalline silicon layer 134.

On the other hand, in the single crystalline silicon layer 1311 of 100nm thick, a collector region of a bipolar transistor doped with a largeamount of n-type impurities, is formed. On the single crystallinesilicon layer 1311, a single crystalline silicon semiconductor layer1312 of e.g., about 100 nm thick is formed. The single crystallinesilicon layer 1312 is doped with a p-type impurity to form a base regionof the bipolar transistor. On the uppermost surface of the depositedsingle crystalline silicon semiconductor layer 1312, an emitter region1313 of a bipolar transistor doped with a n-type impurity is formed. Anemitter electrode is not shown in the figure. On the single crystallinesilicon semi-conductor layer 1312, an insulating film 1315 made of asilicon oxide is formed for electrically isolating a base electrode 1314of polysilicon and an emitter electrode 1316 from each other. The MOStransistor and the bipolar transistor are covered with an insulatingfilm 1317 such as silicon oxide film. On the insulating film 1317, ametal wiring 1318 of a predetermined pattern is formed.

The metal wiring 1318 is connected to a source/drain region and a baseelectrode through a contact hole 1319 formed in the insulating film1317.

The miniaturized MOS transistor shown in FIG. 18 generally employs anLDD structure. Detailed structures of the gate side wall insulatingmaterial and impurity diffusion region are omitted. As the gateelectrode structure, various structures including a gate electrodehaving a polysilicon/metal (silicide) on which a further insulating filmis deposited or a gate electrode formed of a metal, can be employed.However, the explanation of these structures is omitted herein.Furthermore, an impurity structure such as a well structure in thesilicon substrate is not shown.

The aforementioned explanation is the same with respect to the followingfigures.

The feature of the present invention resides in the following points.Although the semiconductor elements having single crystalline siliconsemi-conductor layers different in thickness are formed on the same SOIsubstrate, the insulating films in the element isolation region havealmost the same thickness. Furthermore, since the single crystallinesilicon semiconductor layers having different types of elements such asa MOS transistor and a bipolar transistor have the same height from thesurface, processing can be performed much easier when a wiring layer isformed in a later step.

Now, referring to FIG. 19A to FIG. 21B, how to manufacture the SOI-Silayer on a silicon semiconductor substrate according to the method of atenth embodiment of the present invention, will be explained.

A semiconductor substrate (hereinafter, referred to as SOI (silion oninsulator) substrate) 11 is prepared which is formed by laminating aburied oxide film 12 such as a silicon oxide film and a singlecrystalline silicon film (SOI-Si film) 14 in this order on the surfacethereof. On the SOI substrate 11, a first insulating film 20 such as asilicon oxide or silicon nitride is deposited (FIG. 19A). Subsequently,a photoresist 21 is deposited on the first insulating film 20. Thephotoresist 21 is patterned by lithography so as to remove thephotoresist 21 in a field region while leaving the photoresist 21 in theelement formation region, thereby forming a resist pattern 21 in theelement formation region (FIG. 19B). Using the photoresist pattern 21 asa mask, etching is performed in accordance with anisotopic etching suchas RIE (Reactive Ion Etching) to remove the first insulating film 20 andthe single crystalline silicon film 14 in the element isolating region(FIG. 19C).

Subsequently, the photoresist 21 is removed and then a second insulatingfilm 13 formed of a silicon oxide is deposited on the first insulatingfilm 20 and the element isolating region (FIG. 20A). Then, the secondinsulating film 13 is polished by CMP (Chemical Mechanical Polishing)until the height of the insulating film 13 from the surface of thesubstrate becomes equal to that of the first insulating film 20 (FIG.20B). In this manner, a buried element isolation insulating film 13consisting of the second insulating film 13 is formed in the elementisolating region. Then, the same plane consisting of the firstinsulating film and the element isolation insulating film is coated witha photoresist 23 and subjected to patterning. As a result, a window(photoresist window) 24 is formed on the element region on which a thicksingle crystalline silicon film is designed to be formed (FIG. 20C).Subsequently, etching is performed through the window 24 to remove thefirst insulating film 20 in the window to expose the single crystallinesilicon film 14. Thereafter, the photoresist is removed (FIG. 21A). Inthe etching process, it is preferable that an etching agent or anetching method not etching away the element isolation insulating film 13should be selected. Thereafter, single crystalline silicon is depositedin accordance with a selective epitaxial deposition method on the singlecrystalline silicon film 14 exposed within the photoresist openingportion (window) 24. As a result, a single crystalline silicon film 15is formed on the single silicon film 14. The single crystalline siliconfilm 15 is thicker than the single crystalline silicon film 14 formed inthe element region masked (covered) with the first insulating film 20.

Thereafter, the first insulating film 20 is etched away (FIG. 21B).Then, the next step for forming a transistor in the single crystallinesilicon films 14, 15 is started.

In this way, a plurality of element isolating films 13 are formed whichhave the same height from the semiconductor substrate 11, andsimultaneously, a plurality of element regions having single crystallinesilicon films (SOI-Si layer) different in film thickness.

The thick single crystalline silicon film is formed by a selectiveepitaxial growth method as shown in the above. Alternatively, the thicksingle crystal silicon film may be formed by depositing an amorphoussilicon film, subjecting it to a heat processing to allow epitaxialgrowth of the amorphous silicon film, and removing an unnecessaryportion by CMP.

The window may be formed on the single crystalline silicon film of theelement region to which a thin single crystal silicon film is to beformed. In this case, the single crystalline silicon film of the elementregion, to which a thin single crystalline silicon film is to be formed,is reduced in thickness in a later step. More specifically, the window24 is formed on the element region to which a thick single crystallinesilicon film is designed to be formed in the aforementioned method.Conversely, the window is formed on the single crystalline silicon filmof the element region to which a thin single crystal silicon film is tobe formed. In this case, the first insulating film 20 of the elementregion to which a thin single crystalline silicon film is to be formed,is removed to expose the surface of the single crystalline silicon film14, and the element region is oxidized, thereby reducing the singlecrystalline silicon film.

In the aforementioned method, when the photoresist window 24 is formedon the element region to which the single crystalline silicon film(SOI-Si layer) is formed thick, a photoresist film window is formed inthe bulk formation region, and then, the buried oxide film (BOX) isetched away. In the etched portion, a bulk element such as a bipolartransistor is formed. In this manner, the SOI element and the bulkelement can be integrally formed.

Now, an eleventh embodiment will be explained with reference to FIGS.22A and 22B.

FIGS. 22A and 22B, which are cross-sectional views of manufacturing stepof a semiconductor device, show a manufacturing step of thesemiconductor device shown in FIG. 18.

In the first place, a SOI substrate is prepared in which a laminate filmconsisting of a buried insulating film 142 of a silicon oxide film of500 nm thick and a single crystalline silicon layer of 100 nm thick, isformed on a wafer-form silicon semiconductor substrate 141. Theresultant structure is subjected to an oxidation process at 900° C. toform a silicon oxide film of 6 nm thick. Thereafter, a silicon nitridefilm (SiN) of about 250 nm thick is deposited by a LPCVD method.Furthermore, a silicon oxide film of 100 nm thick is deposited by a CVDmethod. If necessary, the silicon oxide film is densified to cure byapplying a heat treatment. A photoresist is allowed to remain in theelement formation region by a photolithographic method. Using thephotoresist as a mask, the silicon oxide film, SiN film, and siliconoxide film are etched away. Thereafter, the photoresist is removed.Then, using the silicon oxide film as a mask, the single crystallinesilicon layer is etched away by a RIE method. After that, the surfaceoxidation process is performed. Subsequently, the silicon oxide film of500 nm thick is deposited by a LPCD method.

Thereafter, the surface of the silicon oxide film is removed by a CMPmethod. At this time, the surface of the SiN film is slightly removed.At this time, in the element isolation region, an element isolationinsulating film 143 of the silicon oxide film of about 220 nm thick isuniformly formed over the entire surface of the buried insulating filmof the semi-conductor substrate 141. Thereafter, the SiN film is etchedaway with hot phosphoric acid and the silicon oxide film with a dilutehydrofluoric acid to expose the surfaces of the single crystallinesilicon layers 144, 145. A MOS transistor is formed on the singlecrystalline silicon layer 144 and a bipolar transistor is formed on thesingle crystalline silicon layer 145.

Thereafter, a gate insulating film 146 of 6 nm thick is formed andpolysilicon is deposited with a thickness of 60 nm, and furthermore asilicon nitride film of 60 nm thick is deposited. Then, a photoresist isformed only on a portion at which a gate electrode of the MOS transistorto be formed by a photo-lithographic step. A gate electrode 147 formedof a silicon nitride (SiN) film 148 and a polysilicon film is left as agate pattern by a RIE method. At this time, a gate pattern is not formedin the single crystalline silicon layer 145 to which the bipolartransistor is to be formed. Subsequently, the silicon, oxide film or thesilicon nitride film is deposited with a thickness of about 20 nm by aCVD method and RIE is applied to the entire surface. In this way, theside-wall insulating film 149 is left only at the gate side wallportion.

At that time, a thermal oxidation film of about 4 nm thick remains onthe portion excluding the gate portion on the single crystal siliconsemiconductor layer 144 and on the single crystalline siliconsemiconductor layer 145. Subsequently, the photoresist is removed bydoping an n-type impurity into the region of the single crystallinesilicon semiconductor layer 145 in a photolithographic step and anion-doping step, and then, thermal processing for activation isperformed to remove the remaining thermal oxidation film of about 4 nmthick (FIG. 22A). Thereafter, the single crystalline silicon layers1410, 1411 are selectively deposited on the silicon surface with athickness of about 100 nm by an LPCVD method (FIG. 22B).

As a method of forming the single crystal silicon layer can be modifiedin various ways. In the aforementioned embodiment, the singlecrystalline silicon layer is obtained with a predetermined thickness bya selective silicon epitaxial growth technique. In this case, after thesilicon is overfilled by the selective silicon epitaxial growth to thethickness higher than that of element isolation silicon oxide film 143,an unnecessary portion of the silicon may be removed by a CMP technique.Almost the same structure is resulted. Advantages of this method residein that it is easy to control the thickness of silicon and in that aproblem of facet which tends to be generated by the epitaxial growth canbe overcome. In addition, the height of the upper portion of the gateelectrode can be made equal to the height of the element isolationregion.

There is another method having the same advantage as the aforementionedmethod. In this method, amorphous silicon is deposited over the entiresurface, and annealing is made by using the portion in contact with thesingle crystalline silicon layer as a seed. Solid-phase growth is madein this manner and then an unnecessary portion is removed by a CMPmethod. Thereafter, an n-type impurity diffusion region is formed in theregion of the single crystalline silicon layer 1410 and a p-typeimpurity diffusion region is formed in the single crystalline siliconlayer 1411, and then, a base electrode made of polysilicon is formed.Subsequently, an electrically isolated emitter doped with an n-typeimpurity is formed and subsequently an emitter electrode is formed on asilicon semiconductor substrate 1411. Thereafter, the wiring step isperformed to form wiring (See FIG. 18).

In FIG. 22A, the single crystalline silicon layers different inthickness are formed on the same SOI substrates. The insulating films inthe element isolation region have almost the same thickness. In theserespects, the semiconductor device of the present invention can berealized. Furthermore, since processing is made so as to form thesurfaces of the single crystalline silicon layers appropriately at thesame height, a contact hole can be formed by a simple processing. In thestep of forming a wiring structure, there are a larger stepped portion dof wiring between the MOS transistor region 10 and the bipolartransistor region 11 in the conventional semiconductor device shown inFIG. 23.

The stepped portion d is due to the height h1 of an extension electrodeof a bipolar transistor and the difference h2 in height between theelement isolation insulating film 6 of the bipolar transistor region 9and the element isolation insulating film 5 of the MOS transistor region10 (d=h1+h2).

If the stepped portion is too large, the lithography is not accuratelyperformed and the coverage with the insulating film is not sufficient onthe other hand, there is no stepped portion in the cross-sectional viewof a conventional semiconductor device shown in FIG. 24, so that thesurface is flat. However, there is a large difference in depth (T2−T1)between a contact hole in which connecting wiring for electricallyconnecting the wiring to the source/drain region of a MOS transistor isburied and a contact hole in which connecting wiring for electricallyconnecting between the wiring and base electrodes of the bipolartransistor. It is therefore difficult to form the contact hole byetching and metal coverage is not sufficient. The connecting wiring isnot sufficiently deposited in a deep contact hole, frequently causing awire breakage.

In contrast, in the present invention, there is a stepped portion “d”which is the same as the thickness t of the base electrode, as shown inFIG. 18. Therefore, the out-of-focus rarely occurs in a lithographicstep. In addition, it is easy to form contact holes by etching.Micro-processing can be performed without difficulties.

Since the present invention has the aforementioned structures, thefollowing functional effects can be obtained.

Wire-processing is easily performed since the element isolationinsulating films are formed at the same height. Therefore, the yield andreliability are improved. Since a wide focus margin is formed by thephotolithography applied to the element isolation insulating film, microprocessing can be easily made.

It is possible to form different circuits by using elements different indesign policy with the most desirable element structures. The differentIPs are integrated in the same SOI substrate to improve the performanceof a semiconductor device.

It is easy to design a circuit when the circuits operated at powersource voltages of two types or more are integrated in the same SOIsubstrate.

It is possible to attain a circuit different in threshold value andcut-off property without increasing the number of process steps.

It is possible to integrate a plurality of types of desirablesemiconductor elements on the same SOI substrate.

It is possible to reduce the number of process steps.

As described, according to the present invention, since the heights ofthe element isolation insulating films are almost the same, the wiringprocessing can be easily performed, improving the yield and reliability.Since a focus margin can be formed wide by the photolithography appliedto the element isolation insulating film, the micro processing can beperformed easily. Since the surfaces of the single crystalline siliconlayers are formed at the same height, the contact holes can be formedeasily.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A method of manufacturing a semiconductor device comprising: forminga laminated film structure on a semiconductor substrate, by laminating aburied insulating film, a single crystalline semiconductor layer, afirst insulating film subsequently in this order on the semiconductorsubstrate; etching the first insulating film and the single crystallinesemiconductor layer to form a plurality of separated film-laminatesformed of the single crystalline semiconductor layer and the firstinsulating film on the buried insulating film; forming a secondinsulating film on the laminated film structure to cover thefilm-laminates; flattening the second insulating film until a height ofthe second insulating film from the semiconductor substrate becomes thesame as that of the first insulating film to form an element isolationregion; etching the first insulating film of at least a first one of thefilm-laminates to expose the single crystalline semiconductor layerunder the first insulating film of said at least a first one of thefilm-laminates; forming a MOS transistor on the exposed singlecrystalline semiconductor layer of said at least first one of thefilm-laminates; etching the first insulating film of at least a secondone of the film-laminates to expose the single crystalline semiconductorlayer under the first insulating film of said at least a second one ofthe film-laminates; depositing single crystalline semiconductor layersof a predetermined thickness on the single crystalline semiconductorlayers having the MOS transistor formed thereon of said at least a firstone of the film-laminates and on the exposed single crystalsemiconductor layer of said at least a second one of the film-laminates;and forming a bipolar transistor on the deposited single crystallinesemiconductor layer on the exposed single crystal semiconductor layer ofsaid at least a second one of the film-laminates.
 2. A method ofmanufacturing a semiconductor device comprising: forming a laminatedfilm structure on a semiconductor substrate, by laminating a buriedinsulating film, a first single crystalline semiconductor layer, a firstinsulating film subsequently in this order on the semiconductorsubstrate; selectively etching the first insulating film and the firstsingle crystalline semiconductor layer to form a plurality of separatedfilm-laminates formed of the first single crystalline semiconductorlayer and the first insulating film on the buried insulating film;forming a second insulating film on the laminated film structure tocover the film-laminates; flattening the second insulating film until aheight of the second insulating film from the semiconductor substratebecomes the same as that of the first insulating film to form an elementisolation region; etching the first insulating film of at least a firstone of the film-laminates to expose the first single crystallinesemiconductor layer under the first insulating film of said at leastfirst one of the film-laminates; depositing a second single crystallinesemiconductor layer of a predetermined thickness on the exposed firstsingle crystalline semiconductor layer of said at least first one of thefilm-laminates; etching the first insulating film of at least a secondone of the film-laminates to expose the first single crystallinesemiconductor layer under the first insulating film of said at leastsecond one of the film-laminates; and forming a first MOS transistor onthe second single crystalline semiconductor layer on the exposed firstsingle crystalline semiconductor layer of said at least first one of thefilm-laminates and a second MOS transistor on the first singlecrystalline semiconductor layer of said at least second one of thefilm-laminates.
 3. A method of manufacturing a semiconductor devicecomprising: forming a laminated film structure on a semiconductorsubstrate, by laminating a buried insulating film, a first singlecrystalline semiconductor layer, a first insulating film subsequently inthis order on the semiconductor substrate; selectively etching the firstinsulating film and the first single crystalline semiconductor layer toform a plurality of separated film-laminates formed of the first singlecrystalline semiconductor layer and the first insulating film on theburied insulating film; forming a second insulating film on thelaminated film structure to cover the film-laminates; flattening thesecond insulating film until a height of the second insulating film fromthe semiconductor substrate becomes the same as that of the firstinsulating film to form an element isolation region; etching the firstinsulating film of at least a first one of the film-laminates to exposethe first single crystalline semiconductor layer under the firstinsulating film of said at least first one of the film-laminates;depositing a second single crystalline semiconductor layer of apredetermined thickness on the exposed first single crystallinesemiconductor layer of said at least first one of the film-laminates;etching the first insulating film of at least a second one of thefilm-laminates, leaving a portion of the first insulating film by apredetermined thickness; and forming a first MOS transistor on thesecond single crystalline semiconductor layer on the exposed firstsingle crystalline semiconductor layer of said at least first one of thefilm-laminates and a second MOS transistor on the first singlecrystalline semiconductor layer of said at least second one of thefilm-laminates, by carrying out oxidation to form first and second gateinsulation films of the first and second MOS transistors, respectively,and deposition to form first and second gate electrodes of the first andsecond MOS transistors, respectively, the second gate insulation film ofthe second MOS transistor being thicker than the first gate insulationfilm of the first MOS transistor.